Brake control system defined by field programmable gate arrey

ABSTRACT

A brake control system for a wheeled vehicle includes a field programmable gate array configured to perform the algorithm of brake control subsystems in a typical brake control system for a wheeled vehicle. The brake control subsystems typically include anti-skid control, brake temperature monitoring, built-in tests, and, in the case of an aircraft, nose wheel steering. The system also includes wheel speed sensors, brake temperature monitors, brake valves and associated control circuits, and brake valve monitors respecting brake valve current and voltage. The use of field programmable gate arrays to configure a brake control system avoids the obsolescence and shortened life of control systems previously dependent upon microprocessors and the like.

TECHNICAL FIELD

[0001] The invention herein resides in the art of electronic controlsystems and, more particularly, to control systems for aircraft brakes.Specifically, the invention relates to a brake control system defined byfield programable gate arrays and application specific integratedcircuits such as to provide a hardware implementation of a softwarebased brake control/anti-skid algorithm, including brake-by-wire,automatic braking, and brake temperature monitoring. The invention isgenerally applicable to a broad range of control systems, of whichaircraft brakes are simply an example.

BACKGROUND ART

[0002] The invention presented in detail herein is set forth withrespect to an aircraft braking system and, more specifically, to theanti-skid control portion of such a braking system. The invention,however, contemplates adaptation to a broad range of controls in whichfield programmable gate arrays may be employed for purposes which willbecome apparent herein.

[0003] In the prior art of control systems, and particularly those foraircraft brakes, the control system was devised of circuitry comprisingdiscrete components. Over a course of time, such aircraft brake controlsystems evolved to the implementation of dedicated microprocessors orelectronic chips, such that the control system design was primarilysoftware controlled and algorithm dependent. The market for electronicchips has been substantially consumer driven, with little thought toafter-market support. Accordingly, the expected life for many electronicsystems is on the order of five years. New high density, high speedcomponents are expected to have operational lives on the order of aboutseven years. While this is happening “MIL-spec” parts are being removedfrom production. But, airframe manufacturers expect the avionics of theaircraft to last and be supported for the life of the aircraft—often onthe order of thirty years or more.

[0004] Current market trends exacerbate the problem of obsolete parts.The avionics industry, and others as well, are thus driven to change theway they do business. While consideration may be given to life-time buys(purchasing and maintaining an adequate quantity of electronics parts toservice the aircraft from the beginning), such an approach is bothexpensive and risky. Similarly, periodic redesigns to obtain the samefunctionality are costly and time consuming. A better approach is toembrace a new technology that is flexible and has a long period ofprojected availability.

[0005] Field Programmable Gate Arrays (FPGA), though not previouslyapplied to control systems in general or braking systems in particular,have been found to be attractive to fit the avionics needs of theaircraft industry. It is presently anticipated that FPGA's are projectedto be available for a long period of time. They are cost effective, theyare both scalable and flexible in application, they involve a low tomoderate risk factor, and they serve to reduce dependency onmicroprocessors that are given to obsolescence.

DISCLOSURE OF INVENTION

[0006] In light of the foregoing, it is a first aspect of the inventionto provide a control system defined primarily by field programmable gatearrays in order to avoid the obsolescence and shortened life of suchcontrol systems previously dependent upon microprocessors and the like.

[0007] Another aspect of the invention is the provision of a brakecontrol system defined by FPGA's, including all portions thereofpreviously dependent upon software or algorithm configurations.

[0008] Still a further aspect of the invention is the provision of abrake control system defined by FPGA's, in which all subsystems of thebrake control system, such as anti-skid, nosewheel steering, braketemperature monitoring, built-in tests, and the like are all implementedthrough FPGA's or application specific integrated circuits (ASIC).

[0009] The foregoing and other aspects of the invention which willbecome apparent as the detailed description proceeds are achieved by abrake control system for an aircraft in which the various subsystems andcomponents thereof, such as filters, integrators, amplifiers and thelike are all replicated by FPGA's which thereby provide a hardwareimplementation of what was previously configured in software in priorsystems.

[0010] Other aspects of the invention are attained by a brake system fora wheeled vehicle comprising: a field programmable gate array configuredto perform an algorithm of brake control subsystems taken from the groupcomprising anti-skid control, nosewheel steering, brake temperaturemonitoring, and built-in tests; a wheel speed interface interposedbetween wheel speed transducers of said wheeled vehicle and said fieldprogrammable gate array for presenting signals to said fieldprogrammable array corresponding to instantaneous wheel speed; and abrake temperature interface interposed between brakes of said vehicleand said field programmable gate array and providing signalscorresponding to brake temperature.

DESCRIPTION OF THE DRAWINGS

[0011] For a complete understanding of the objects, techniques andstructure of the invention reference should be made to the followingdetailed description and accompanying drawings wherein:

[0012]FIG. 1 is a block diagram of a brake control system made inaccordance with the invention;

[0013]FIG. 2 is a circuit schematic of the anti-skid simulation of thecontrol system of FIG. 1;

[0014]FIG. 3 is a schematic diagram of the FPGA design of a low passfilter employed in the subsystem of FIG. 2; and

[0015]FIG. 4 is a schematic diagram of the FPGA implementation of asecond order low pass filter employed in the embodiment of FIG. 2.

BEST MODE FOR CARRYING OUT THE INVENTION

[0016] Referring now to the drawings and more particularly to FIG. 1, itcan be seen that a brake control system made in accordance with theinvention is designated generally by the numeral 10. Again, while theconcept of the invention is described in the context of an aircraftbrake control system, it will be appreciated that the general concept isapplicable to a broad range of control structures.

[0017] At the heart of the brake control system 10 is a fieldprogrammable gate array (FPGA) 12, which is of sufficient size toaccommodate the functions to be performed by the brake control system10. A wheel speed interface 14 is interconnected between wheel speedtransducers and the FPGA 12 to provide wheel speed signals of afrequency corresponding to instantaneous wheel speeds in a manner wellknown and understood by those skilled in the art. Similarly, a braketemperature interface 16 may be interconnected to an appropriatetemperature sensor such as thermocouple, thermistor or the like, toreceive signals corresponding to brake temperature. The output of thebrake temperature interface 16 is provided to an appropriate analogcomparator 18 which serves as a brake temperature monitoring system,providing outputs to the FPGA 12, as shown.

[0018] A second analog comparator 20 is interconnected with anti-skidbrake valves to monitor the valve voltage and valve current and toprovide corresponding outputs relevant thereto to the FPGA 12, as shown.A third analog comparator 22 is shown for such other monitoringfunctions as might be desired. Those skilled in the art will appreciatethat the monitoring of valve voltages and currents, as well as braketemperature is a common and necessary undertaking in most brake controlsystems, the comparator 22 being provided for such additional monitoringas may be desired.

[0019] A buffer 24 is provided to receive external signals such as aweight on wheels signal or the like to provide such inputs to the FPGA12 as desired.

[0020] A clock 26 and watchdog timer 28 are provided in association withthe FPGA 12 for purposes of synchronous operation and timing. A programmemory input 30 is interconnected to a program serial port forprogramming of the FPGA 12 to operate in accordance with a desiredalgorithm. The programming of FPGA's is well known and understood bythose skilled in the art and, once the appropriate transfer functionsare established, may be readily implemented.

[0021] An array of discrete output buffers 32 is provided for monitoringcontrol matters such as wheel speed as determined from transducerinterface 14, or further monitoring wheel spin-up signals and the likefrom external sources. The valve control signals are pulse widthmodulation outputs of the FPGA 12 and are provided through filters 34,36and appropriate valve drivers 38, 40 to the anti-skid valves in theembodiment shown. The outputs of the valve drivers are introduced as thevalve voltage and current signals applied to the analog comparator 20.Similarly, the pulse width modulated output from the FPGA 12 is passedthrough the filter 42 and to the various analog comparators 18, 20, 22to establish the referenced analog ramp signal to be employed by suchcomparators in their operative modes.

[0022] Filters 44, 46 receive outputs from the FPGA 12 corresponding tothe wheel speed signals of associated wheels and pass those signals toperipheral equipment as desired. Similarly, outputs from serial ports ofthe FPGA 12 are passed to appropriate peripheral equipment such asbuilt-in test equipment and the like.

[0023] Fundamentally, it should be appreciated that FIG. 1 provides theoverall structure of a brake control system, with the FPGA 12 serving toperform the algorithm of the various subsystems thereof. One suchsubsystem is the anti-skid system, shown in FPGA simulation in FIG. 2and designated generally by the numeral 50. As shown, the wheel speedsignal pulses from the interface 14 are applied to a frequency todigital converter 52 and then passed through a low pass filter 54 to ridthe signal of noise. A second notch filter 56 further refines the signalby eliminating or rejecting signal frequencies attributed to the naturalstrut frequency of the associated wheel. A threshold comparator ordrop-out circuit 58 receives the filtered wheel speed signal and blocksany such signals indicative of wheel speed below a certain threshold. Asis well known to those skilled in the art, it is generally desired thatanti-skid operation be precluded below a particular velocity thresholdsuch as, for example, 16.9 feet per second.

[0024] When operating above the drop out threshold, the filtered wheelspeed signal passes from the circuit 58 to a high pass filter 60 thatoperates as a differentiator to generate a signal corresponding to wheeldeceleration. That signal is then passed to a second high pass filter 62which, operating as a differentiator, generates the second derivative ofwheel speed, the same being a signal corresponding to the rate of changeof deceleration. Those skilled in the art will appreciate that theoutput of the second high pass filter 62, corresponding to the rate ofchange of deceleration, is employed to anticipate skids by theassociated wheel. A limiter circuit 64 responds to the output of thehigh pass filter 62 and limits the output thereof such that theanti-skid system responds only to the initiation of the secondderivative output from the circuit 62, such that the second derivativeis an initiating, but not a driving force in the anti-skid operation.

[0025] The output of the limiter 64 is passed, along with the output ofthe modulator 72 to a summing circuit 66, the output of which is theinstantaneous average of the wheel speed signal. The output of thesumming circuit 66 passes through a non-linear gain control circuit 68an then to the multiplexer 70, the output of which passes to the valvedriver of the anti-skid valve.

[0026] Also included as part and parcel of the anti-skid FPGA simulation50 is a skid detector 74, receiving the filtered wheel speed signal fromthe notch filter 56. As will be appreciated by those skilled in the art,the skid detector 74 detects instantaneous large changes in wheel speed,identifies the same, and passes such signals to the multiplexer 70 forand instantaneous release of brake pressure, if necessary. The output ofthe skid detector 74 is also passed to the modulator 72 to charge themodulator which, as is known to those skilled in the art, is anintegrator establishing an output signal, applied to the anti-skidvalve, corresponding to the average skid activity of the associatedwheel. In this regard, the output of the skid detector 74 is passedthrough staged gain control circuits 76 to the modulator 72. A timer 78is interposed to delay any transfer of signals which might be attributedto strut reaction to braking activity from the first differentiator tothe modulator 72 immediately after the skid detector turns off. In otherwords, the timer 78 allows a delay in signal transfer sufficient toallow strut reactions to damp out following skid recovery.

[0027] Also provided as part and parcel of the anti-skid FPGA simulation58 is a high pass filter 80, receiving the deceleration output signal ofthe high pass filter 60. This filter 80 serves to pass all signalsexcept those that have a relatively constant value. The output of thefilter 80 is passed from a second order low pass filter 80 a to arectifier 82 such that the output thereof is a rectified signal(absolute value) corresponding to changes in wheel speed deceleration.The pulses of the rectified signal are passed to a peak detector 84 inwhich sequential data pairs are compared, and the maximum held. Theoutput of the peak detector 84 is passed to the summer 86 and thence tothe modulator 72. Thus, it will be appreciated that the anti-skidcircuit 58 receives a multitude of signals corresponding to skiddingactivity of the associated aircraft wheel. An on/off signal is receivedfrom the skid detector 74, an integrated or average signal is receivedfrom the modulator 72 and an anticipatory or derivative signal isreceived from the differentiators 60, 62.

[0028] Consistent with the concept of the instant invention, theanti-skid control algorithm 58 of FIG. 2 is reduced to fieldprogrammable gate array implementation by employment of appropriatetransfer functions which should be perceived by those skilled in the artof FPGA technology. With reference to FIG. 3, it can be seen that thelow pass filter 54 may be defined by FPGA simulation in the mannerdepicted in FIG. 3. The low pass filter 54 includes a multiplier oramplifier 90 interconnected to an adding circuit 92, the output of whichis fed back through an amplifier 94 to a subtracting circuit 96, theoutput of which passes through a sample period delay circuit 98 and isthen fed to the summer or adding circuit 92. Those skilled in the artwill appreciate that FIG. 3 presents the block set for the low passfilter 54 which, when appropriately scaled in accordance with thedesired transfer function, will allow the FPGA 12 to be properly routedto perform the low pass filter function.

[0029] The block set 70 for the second order low pass filter 80 a ofFIG. 2 is shown in FIG. 4. The input passes to a multiplier or amplifier100 which passes to an adder or summing circuit 102, the output of whichpasses to a subtracting circuit 104 which includes a feedback circuit ofsample delays 106, 108 and multiplier or amplifier 110. A secondfeedback circuit interconnects the output of the substracter 104 and theadder 102 through the sample delay 106 and amplifier or multiplier 112.Again, those skilled in the art will appreciate that implementation ofappropriate scaling and transfer functions will allow the FPGA 12 to beproperly routed to perform the functions set forth in FIG. 4 to achievethe desired second order low pass filter configuration.

[0030] Each of the various functions of the anti-skid simulation of FIG.2 may be reduced to a block set with appropriate scaling and transferfunctions to allow for the appropriate routing of the FPGA 12 to performthe associated functions. Accordingly, the entirety of the anti-skidfunction of FIG. 2 can be incorporated into the structure of the FPGA12. In like manner, other subsystems of the brake control system 10 canbe similarly reduced to an FPGA implementation, such as nose wheelsteering, automatic braking, brake temperature monitoring, and the like.

[0031] Thus it can be seen that the objects of the invention have beensatisfied by the structure presented and described above. The algorithmsof the brake control system can be reduced to the desired scaling andtransfer functions necessary to implement an FPGA routing to accomplishthe necessary function, thereby alleviating the need for discretecomponents or electronic chips given to obsolescence.

What is claimed is:
 1. A brake control system for a wheeled vehicle,comprising: a field programmable gate array configured to perform analgorithm of brake control subsystems taken from the group comprisinganti-skid control, nosewheel steering, brake temperature monitoring, andbuilt-in tests; a wheel speed interface interposed between wheel speedtransducers of said wheeled vehicle and said field programmable gatearray for presenting signals to said field programmable arraycorresponding to instantaneous wheel speed; and a brake temperatureinterface interposed between brakes of said vehicle and said fieldprogrammable gate array and providing signals corresponding to braketemperature.
 2. The brake control system according to claim 1, furthercomprising a coparator interposed between anti-skid brake valves andsaid field programmable gate array, said comparator providing signals tosaid field programmable gate array corresponding to anti-skid brakevalve current and voltage.
 3. The brake control system according toclaim 2, wherein said field programmable gate array provides brakecontrol signals to said anti-skid valves.
 4. The brake control systemaccording to claim 2, wherein said field programmable gate arrayprovides brake control signals to said anti-skid valves.
 5. The brakecontrol system according to claim 1, wherein said anti-skid controlsubsystem comprises: a frequency to digital converter receiving wheelspeed signals and passing said wheel speed signals through low pass andnotch filters, generating filtered wheel speed signals; first and secondinterconnected differentiators receiving said filtered wheel speedsignals, generating first and second derivatives of wheel speed.
 6. Thebrake control system according to claim 4, wherein said anti-skidcontrol system further comprises a limiter connected to said first andsecond interconnected differentiators for limiting the signalcorresponding to the second derivative of wheel speed.
 7. The brakecontrol system according to claim 5, wherein said anti-skid controlsystem further comprises a modulator operatively connected to ananti-skid valve driver and providing thereto an instantaneous averagewheel speed signal.
 8. The brake control system according to claim 6,wherein said anti-skid control system further comprises a skid detectorpassing output signals corresponding to instantaneous large changes inwheel speed to said anti-skid brake control valve driver and saidmodulator.